Complexity Of Minimum-Delay Gate Resizing

Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gate-level circuits. In this paper , we study the complexity of two diierent minimum-delay gate resizing problems for combinational circuits composed of single-output gates. The rst problem is that of gate resizing for minimum circuit delay under the load-dependent delay model. The second problem is a variant of the rst, where we relax the delay model to a load-independent one, but impose load constraints instead , i.e., each gate output is not allowed to drive a capacitive load that exceeds its drive capacity. The goal, as before, is to minimize the delay through the circuit. To the best of our knowledge, there has been no published result on the complexity of these problems. In this paper, we prove that both problems are NP-complete. The proofs are inspired by Murgai's work 6], in which the global fanout optimizationproblem under a xed net topology was shown to be NP-complete. These results, along with previously published ones, establish that gate resizing is a hard problem except under the most simplistic assumptions. 1 Motivation Gate resizing for minimum circuit delay is a fundamental problem in performance optimization of gate-level circuits. Ideally, each gate should be optimally sized during technology mapping. However , exact technology mapping is expensive in practice due to the large size of the technology library and due to the complex interaction between the gate being mapped and the unmapped portion of the logic. In addition, wire loads often cannot be estimated with suucient accuracy during technology mapping to make the best choices for gate sizes. As a result, heuristics are used, which, among other things, may not select the best sizes for gates from a delay perspective 3]. This leaves scope for improving the circuit delay by resizing gates after technology mapping. Being an in-place optimization technique, gate resizing is also layout-friendly (i.e., it does not disturb placement and routing of cells) and can be used during or after layout when more accurate wire load and delay information is available. Thus, gate resizing has become an important optimization problem in its own right. The complexity of timing optimization problems, such as gate resizing or technologymapping for minimum circuit delay, depends on the delay model used in the analysis. Two commonly used delay models in gate-level circuits are: the load-independent delay model (LIDM) and the load-dependent delay …